In the design of semiconductor integrated circuits (ICs) it is often desirable to provide a mixed mode device, i.e, which has both BJT and CMOS functions. Mixed mode devices both increase the flexibility of the IC design and increase the performance of the IC. When the performance of the BJT aspect of the mixed mode device is of concern, then a BiCMOS process is typically required. When the performance of the BJT aspect of the mixed mode device is not a priority, a parasitic BJT is formed in a CMOS structure. Generally speaking, the BiCMOS process is more complex and expensive than the CMOS process.
FIG. 1 shows a typical parasitic NPN vertical BJT 10. The vertical BJT 10 has a N.sup.+ emitter region 12. Two P.sup.+ base contact regions 16 and 18 are formed in a P-type base region 20. The base region 20, itself, is formed in P-well 20, above an N-type collector region 24. An N.sup.+ contact 26 is provided for the collector region 24 in the N-well 22, between two field oxide (fox) regions 28 and 30 (which may be SiO.sub.2 regions).
The conventional vertical BJT 10 has two significant design limitations. First, the BJT 10 has a great base width W.sub.b which is equal to the depth of the P-well 22. Second, the vertical BJT architecture has a common collector structure. Such a structure provides for low current gain which is sometimes desirable. However, the vertical BJT 10 is restricted to common collector applications.
FIG. 2 shows a first conventional lateral BJT architecture 40. The NPN lateral BJT 40 has similarities to a CMOS device. That is, the lateral BJT 40 has a poly region 42 formed on a thin gate oxide layer 43. The thin gate oxide layer 43, itself, is formed on a P well 48 which is formed in an N-type substrate 50. An N.sup.+ emitter contact region 44 is provided adjacent to an N.sup.- emitter region 45 and an N.sup.+ collector contact region 46 is provided adjacent to an N.sup.- collector region 47. The emitter and collector regions 44/45, and 46/47 are very similar to drain and source regions. However, in this case, the bulk of the P well 48 functions as a base. In fact, a P.sup.+ base contact region 52 may be provided. The poly region 42 is typically grounded (as shown in phantom) or left floating.
The lateral BJT architecture 40 has two disadvantages. First, the lateral BJT 40 has a great base width W.sub.b which extends between the emitter 44/45 and collector 46/47 regions. This base width is limited by the width of the poly region 42 which in turn is limited by the photolithographic resolution of the fabrication process used to form the poly region 42. Second, the collector region 46/47 is only as deep as the emitter region 44/45. Thus, the collector 46/47 does not collect efficiently.
FIG. 3 shows a second lateral BJT architecture 60. The NPN lateral BJT 60 has a P well 62 formed in an N-type substrate 64. As before, an N.sup.+ emitter region 68 and an N.sup.+ collector region 70 are formed in the P well 62, wherein the bulk of the P well functions as the base. A P.sup.+ base contact 74 may also be provided. Unlike before, the emitter 68 and collector 70 regions are separated by a fox region 72 formed on the surface of the P well 62.
The lateral BJT architecture 60 also has a great base width W.sub.b. In this case, W.sub.b is approximately equal to the size of the fox region 72, which size is limited by the photolithographic resolution of the fabrication process used to form the fox region 72. In addition, the fox region 72, which intrudes into the P well 62 affects the base width W.sub.b. Thus, it is difficult to fabricate a lateral BJT 60 having particular desired characteristics with a high manufacturing tolerance.
It is therefore the object of the present invention to overcome the disadvantages of the prior art. It is also an object of the present invention to provide a mixed mode device which can be manufactured using CMOS compatible processes.